Method for Manufacturing Magnetoresistance Component

ABSTRACT

A method for manufacturing a magnetoresistance component is provided. A substrate is provided. A circuit structure layer including an interconnect structure is formed on the substrate, wherein the interconnect structure comprises a metal pad. A dielectric layer is formed on the circuit structure. A metal damascene structure is formed in the dielectric layer. A patterned magnetoresistance component is formed above the metal damascene structure to electrically connect to the metal damascene structure.

FIELD OF THE INVENTION

The present invention relates to a method for manufacturing amagnetoresistance component, and particularly to a method formanufacturing an integrated circuit structure with a magnetoresistancecomponent.

BACKGROUND OF THE INVENTION

Recently, a magnetoresistance component has been widely employed forelectronic apparatuses because the magnetoresistance component has afunction of changing the value of its electrical resistance with thevariation of an external magnetic field applied to it. Generally, it isnecessary for the magnetoresistance component to be cooperated with aperipheral integrated circuit to achieve its function. Thus, it isdesired that the magnetoresistance component can be integrated with theperipheral integrated circuit on a common substrate in an integratedcircuit manufacturing process. However, in a typical integrated circuitmanufacturing process, it is difficult to integrate themagnetoresistance component with the peripheral integrated circuit on acommon substrate on condition that the performance of themagnetoresistance component is not affected.

SUMMARY OF THE INVENTION

The present invention provides a method for manufacturing an integratedcircuit structure with a magnetoresistance component so that themagnetoresistance component can be easily integrated with an integratedcircuit on a common substrate and the performance of themagnetoresistance component is not affected.

The present invention provides a method for manufacturing amagnetoresistance component. A substrate is provided. A circuitstructure layer including an interconnect structure is formed on thesubstrate, wherein the interconnect structure comprises a metal pad. Adielectric layer is formed on the circuit structure layer. A metaldamascene structure is formed in the dielectric layer. A patternedmagnetoresistance component is formed above the metal damascenestructure to electrically connect to the metal damascene structure.

BRIEF DESCRIPTION OF THE DRAWINGS

The above objects and advantages of the present invention will becomemore readily apparent to those ordinarily skilled in the art afterreviewing the following detailed description and accompanying drawings,in which:

FIGS. 1A to 1D illustrates a process flow of a method manufacturing anintegrated circuit structure with a magnetoresistance component inaccordance with an embodiment of the present invention.

FIG. 2 illustrates a metal damascene structure formed in a dielectriclayer in accordance with another embodiment of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The present invention will now be described more specifically withreference to the following embodiments. It is to be noted that thefollowing descriptions of preferred embodiments of this invention arepresented herein for purpose of illustration and description only. It isnot intended to be exhaustive or to be limited to the precise formdisclosed.

FIGS. 1A to 1D illustrates a process flow of a method manufacturing anintegrated circuit structure with a magnetoresistance component inaccordance with an embodiment of the present invention. Referring toFIG. 1A, a substrate 1 is provided. A circuit structure layer 10 forexample a metal interconnection structure layer is formed on thesubstrate 1. The circuit structure layer 10 for example the metalinterconnection structure layer can include a circuit (not shown) suchas a set circuit, a reset circuit or an offset circuit. It is notedthat, the circuit structure layer 10 also includes a metal pad 100. Adielectric layer 11 is formed on the circuit structure layer 10. Thedielectric layer 11 can be a single layer structure or a multiple layerstructure. For example, the dielectric layer 11 can be a silicon oxidelayer, a silicon nitride layer, or a combination thereof on the circuitstructure layer. In the present embodiment, the dielectric layer 11 isthe multiple layer structure including a silicon oxide layer 110, asilicon nitride layer 111, and a silicon oxide layer 112. The siliconoxide layer 110, the silicon nitride layer 111, and the silicon oxidelayer 112 are formed on the circuit structure layer 10 in that order. Ametal damascene structure 113 here refers to a metal structure embeddedin the dielectric layer 11 with an exposed top surface. The metaldamascene structure 113 is in direct contact with a magnetoresistancecomponent 115 formed in a subsequent step. The exposed top surface ofmetal damascene structure 113 is configured either partially or fullyenclosed by the magnetoresistance component 115. The patterns of themetal damascene structure 113 can be line-shaped or a large area withslots. The metal damascene structure 113 is electrically connected tothe magnetoresistance component 115 only or provides an electricalconnection between the magnetoresistance component 115 and the circuitstructure layer 10. In the present embodiment, the metal, damascenestructure 113 is formed by using a conventional single-damascene process(as shown in FIG. 1A). In another embodiment, the metal damascenestructure 113 can be formed by a dual-damascene process (as shown inFIG. 2). In such cases the metal damascene structure 113 is made oftungsten or copper.

In still another embodiment, the metal damascene structure 113 can beformed by forming a metal structure first, followed by a dielectricdeposition and polishing process. In the dielectric deposition andpolishing process, a dielectric material layer is formed on the metalstructure and then is polished for planarization to form the dielectriclayer 11 and expose a top surface of the metal structure. The metalstructure can be made of conventional metallic materials which can bepatterned by chemical etch, such as pure elements or alloys comprisingaluminum, titanium, and tantalum.

Still referring to FIG. 1A, during formation of the metal damascenestructure 113, a planarization process is generally performed. Thus, atop surface of the dielectric layer 11 and a top surface of the metaldamascene structure 113 form a common flat plane, which is beneficialfor the performance of magnetoresistance component 115. However, tooflat top surfaces may not be convenient for a subsequentphotolithography process of forming a magnetoresistance component 115.In the present embodiment, the following steps are further performed sothat the manufacturing inconvenience caused by the flat top surfaces canbe solved.

Referring to FIG. 1B, a number of openings 114 a, 114 b are formed inthe dielectric layer 11 by a photolithography and etching process. Theopenings 114 a, 114 b in the dielectric layer 11 form a number ofstep-drops. The step-drop of the opening 114 a can be located in thescribe line region and configured for defining a number of alignmentmarks for a subsequent photolithography process. The opening 114 b canbe located above the metal pad 100 for the purpose of reducing padetching depth. A depth of the openings 114 a, 114 b can be less than thethickness of the dielectric layer 11. That is, only a portion of thedielectric layer 11 is removed to form the openings 114 a, 114 b. Inanother embodiment, a depth of the openings 114 a, 114 b can be equal tothe thickness of the dielectric layer 11. That is, the dielectric layer11 is completely etched through to form the openings 114 a, 114 b. Instill another embodiment, a depth of the openings 114 a, 114 b can begreater than the thickness of the dielectric layer 11. That is, thedielectric layer 11 is etched through and a portion of the dielectriclayers of the circuit structure layer 10 is removed to form the openings114 a, 114 b.

In the present embodiment, only one magnetoresistance component 115 isshown. In another embodiment, the substrate can define amagnetoresistance array region (not shown) for arranging a number ofmagnetoresistance components. The opening 114 a can also be defined inthe magnetoresistance array region for specific designs of themagnetoresistance components.

Next, referring to FIG. 1C, a magnetoresistance material layer (notshown) is formed on the dielectric layer 11 after forming the openings114 a, 114 b. The magnetoresistance material layer can be a single-layerstructure or a multiple-layer structure. Because the magnetoresistancematerial layer is generally opaque, the alignment marks of previousmetal layers can not be optically recognized through the coverage of themagnetoresistance material layer, thereby losing their alignmentfunction. However, for example, in the present embodiment, the alignmentmark defined by the opening 114 a can still be recognized due to itstopographic (step-drop) signal even an opaque magnetoresistance materiallayer is covered. That is, the step-drop of the opening 114 a can beconfigured for defining the alignment mark for a subsequentphotolithography process. In the present embodiment, a photolithographyprocess using the step-drop alignment mark is applied to pattern themagnetoresistance material layer to form a magnetoresistance component115 electrically connected to the metal damascene structure 113.

Referring to FIG. 1D, next a passivation layer 116 is conformallydeposited to protect the magnetoresistance component 115. Thepassivation layer 116 is configured for preventing the magnetoresistancecomponent 115 from contaminations and damages. The passivation layer 116can be formed by a low thermal budget process. The passivation layer 116can be a single-layer structure or a multiple-layer structure. Forexample, the passivation layer can be a silicon nitride layer, a siliconoxide layer, or a combination thereof on the dielectric layer. In thepresent embodiment, the passivation layer 116 is the multiple layerstructure including a silicon nitride layer 1160, a silicon oxide layer1161, and a silicon nitride layer 1162. The silicon nitride layer 1160,the silicon oxide layer 1161, and the silicon nitride layer 1162 areformed in that order. In other embodiment, the passivation layer 116 canbe the single layer structure including a silicon nitride layer. Next,the passivation layer 116 as well as the dielectric layer 11 above themetal pad 100 can be removed so as to expose the metal pad 100. Due tothe previously formed opening 114 b above the metal pad 100, the etchingamount of the dielectric layer 11 for exposing the metal pad 100 isgreatly reduced.

It is noted that, the substrate 1 can be a silicon substrate or asilicon substrate covered by a dielectric material layer, a silicongermanium (SiGe) layer, a gallium arsenide (GaAs) layer, a siliconcarbide (SiC) layer and so on. It is also noted that, an integratedcircuit, for example, an application-specific integrated circuit (ASIC),a logic integrated circuit, an analog integrated circuit and amixed-mode integrated circuit, can be formed on the substrate 1. Byusing the method according to the present embodiment, as shown in FIG.1D, an integrated circuit structure with the magnetoresistance component115 can be formed. The magnetoresistance component 115 can be ananisotropic magnetoresistance (AMR) component, a giant magnetoresistance(GMR) component, a tunneling magnetoresistance (TMR) component or acolossal magnetoresistance (CMR) component.

While the invention has been described in terms of what is presentlyconsidered to be the most practical and preferred embodiments, it is tobe understood that the invention needs not be limited to the disclosedembodiments. On the contrary, it is intended to cover variousmodifications and similar arrangements included within the spirit andscope of the appended claims which are to be accorded with the broadestinterpretation so as to encompass all such modifications and similarstructures.

What is claimed is:
 1. A method for manufacturing a magnetoresistancecomponent, comprising: providing a substrate; forming a circuitstructure layer comprising an interconnect structure on the substrate,the interconnect structure comprising a metal pad; forming a dielectriclayer on the circuit structure layer; forming a metal damascenestructure in the dielectric layer; and forming a patternedmagnetoresistance component above the metal damascene structure toelectrically connect to the metal damascene structure.
 2. The method ofclaim 1, further comprising : forming a passivation layer on thepatterned magnetoresistance component; removing a portion of thepassivation layer to form an opening exposing the metal pad.
 3. Themethod of claim 1, wherein forming the patterned magnetoresistancecomponent comprises: forming at least one opening in the dielectriclayer; forming a magnetoresistance material layer on the dielectriclayer covering the at least one opening; and patterning themagnetoresistance material layer.
 4. The method of claim 3, whereinforming the dielectric layer comprises: forming a silicon oxide layer;forming a silicon nitride layer on the silicon oxide layer; and forminga silicon oxide layer on the silicon nitride layer.
 5. The method ofclaim 3, wherein the at least one opening is located in a scribe lineregion of the substrate.
 6. The method of claim 3 wherein the at leastone opening is located above the metal pad.
 7. The method of claim 3,wherein the at least one opening is located in a magnetoresistance arrayregion.
 8. The method of claim 3, wherein a part of the patternedmagnetoresistance component is disposed above the dielectric layer. 9.The method of claim 3, wherein the patterned magnetoresistance componentis completely disposed above the dielectric layer.
 10. The method ofclaim 3, wherein the patterned magnetoresistance component is formed bypatterning the magnetoresistance material layer using an alignment mark.